1. Technical Field
The present invention generally relates to phase locked loops and in particular to differential charge pumps in phase-locked loop circuits.
2. Description of the Related Art
When phase locked loops (PLLs) are required to produce multiple output phases, the duty cycle distortion should remain low for the outputs. Commonly, PLLs implement differential charge pumps that provide adequate noise immunity and exhibit the least sensitivity to supply voltage movement. Such differential designs incorporate the use of negative feedback to set and/or control the common-mode voltage level delivered to the voltage control oscillator (VCO) input. Certain types of VCOs, such as current starved delay VCOs, require a differential voltage interface with a tightly controlled common-mode voltage level for proper operation and low duty cycle distortion.
Often, the low pass filter (LPF) which connects to the charge pump's output also serves as the compensation network for the common mode feedback loop. However, the LPF has difficulty satisfying the stability requirements of the charge pump's common-mode feedback loop, while allowing the global PLL loop bandwidth to be high. The complications derive from multiple ‘poles’ residing in the charge pump common mode feedback loop. These poles originate from the LPF and the common-mode buffering circuits.
Buffering circuits utilized in PLLs present ‘poles’ to the charge pump's common mode feedback. When the LPF is the compensation network for the charge pump's common-mode feedback, a wide bandwidth PLL's low pass filter presents stability problems. The stability problems are a result of the additional buffer poles. Charge pumps require common-mode feedback networks to control the common-mode voltage level. Without optimizing the common-mode voltage level, the VCO output may not yield the desired duty cycle duty cycle.